It is the most advanced and scientific cell phone jammer management system

It is the most advanced and scientific  cell phone jammer  management system.
CMOS TTL logic gate circuit came in after the second widely used to develop digital integrated device, from the development trend, due to manufacturing process improvements, CMOS circuit performance may be beyond the TTL to become the dominant logic devices. Operating speed of CMOS circuits can be compared with the TTL, and its power consumption and anti-jamming capability is far superior to the TTL. In addition, almost all of the ultra-large-scale memory devices, and PLD devices are manufactured using CMOS Arts, and lower cost. Early production of CMOS gates for the 4000 series, followed by the development of 4000B series. CMO current TTL-compatible devices such as 74HCT series TTL devices can be used interchangeably with. The following discussion first CMOS inverter, and then introduce other CMO logic gates.  cell phone jammer can prevent prisoners from remote fraud.
First, consider two extreme cases: when vI is logic 0, the corresponding voltage of approximately 0V; and when vI is logic 1, the corresponding voltage is approximately VDD. Assumed in both cases N-channel tube TN P-channel tube for the working tube pipe TP as loads. However, because the circuit is a complementary symmetry, this assumption can be arbitrary, the opposite situation will lead to the same result. The following diagram analysis of the time when vI = VDD work. The output characteristics of the TN iD-vDS (vGSN = VDD) (Note vDSN = vO), the superposition of a load line, which is the load pipe TP in vSGP = 0V when the output characteristics of iD-vSD. As vSGP <VT (VTN = | VTP | = VT), the load curve is almost a horizontal line coincident with the horizontal axis. Intersection of two curves that the operating point. Obviously, when the output voltage vOL ≈ 0V (typically <10mV, the current through two close to zero.  cell phone jammer intelligent management system can effectively solve the above problems.
It can be seen, the basic CMOS inverter is similar to an ideal logic unit, the output voltage is close to zero or + VDD, while the power is almost zero. The figure below shows the transmission characteristics of CMOS inverter diagram. Figure VDD = 10V, VTN = | VTP | = VT =
2V. As VDD> (VTN + | VTP |), so when VDD-| VTP |> vI> VTN when, TN and TP two shoot-through. Taking into account the complementary symmetrical circuit is a device to another device as it will drain load. Should also be noted that the device in the active region (saturation region) showed constant features, one of two devices can be used as a high resistance load.